1. Field of the invention
The present invention is directed to a semiconductor memory device and a method for manufacturing the same, and more particularly to a semiconductor memory device enabling a reduction of a memory cell in size and a method for manufacturing the same.
2. Description of the Related Art
Since unit cell of DRAM(Dynamic Random Access Memory) basically consists of one transistor and one capacitor, there is benefit that an area occupying the unit cell thereof is small. For manufacturing such DRAM, should be performed four-times polysilicon deposition process; a first polysilicon deposition process for a word line, a second polysilicon deposition process for a bit line, a third polysilicon deposition process for a storage node of a capacitor and a fourth polysilicon deposition process for a plate node of the capacitor. Therefore, the manufacturing process of the DRAM is complicated. Further, a read access port and a write access port both are connected to one data line, so an operation of the DRAM as a logic device is complicated.
In order to remove the above mentioned drawbacks, a method for manufacturing the DRAM by one-step polysilicon deposition process had been proposed.
In FIG. 1, DRAM has a pass transistor for writing, a pass transistor for reading, a storage transistor, a capacitor, word lines for driving the pass transistors and bit lines intersecting the word lines for a data-in and data-out. M1 represents the pass transistor for writing, M2 the storage transistor and M3 the pass transistor for reading. Word line WL1 for reading is connected to a gate of the read pass transistor M3. Word line WL2 for writing is connected to a gate of the write pass transistor M1. Bit line BL1 for writing is connected to a source of the write pass transistor M1. Bit line BL2 for reading is connected to a source of the read pass transistor M3. A drain of the write pass transistor M1 is connected to a gate of the storage transistor M2. A drain of the storage transistor M2 is connected to a drain of the read pass transistor M3. A source of the storage transistor is connected to a Vss voltage terminal. A parasitic capacitor C1 is formed between the drain of the write pass transistor and the gate of the storage transistor. As a capacitance of the capacitor C1 is increased, an amount of data stored in DRAM is increased.
A semiconductor memory device including a circuit of FIG. 1 is designed to determine that if Vss voltage level is detected through the bit line, data is stored in the DRAM cell or if the voltage level over Vss voltage level is detected, no data is in the DRAM cell.
In writing operation, the write word line WL2 is accessed and the write pass transistor M1 is turned on. Accordingly, data at the write bit line BL1 is, through the write pass transistor M1, stored in the capacitor C1.
In reading operation, the read word line WL1 is accessed and the read pass transistor M2 is turned on. The storage transistor M2 is turned on or off in response to data stored in the capacitor C1. If data is previously stored in the capacitor C1, the storage transistor C1 is turned on and the Vss voltage level is detected at the read bit line BL2. Otherwise, if no data is stored in the capacitor C1, the storage transistor M2 is turned off and the voltage level over Vss voltage level is sensed at the read bit line BL2.
FIG. 2 is a view showing a layout of DRAM in FIG. 1. Y1 and Y2 each represents DRAM cell unit area. A1 stands for a first active region on which the storage transistor M2 and the read pass transistor M3 are formed. A2 stands for a second active region on which the write pass transistor M3 is formed. 4A indicates a gate of the write pass transistor M1, 4B a gate of the storage transistor M2 and 4C a gate of the read pass transistor M3. Particularly, a width of the gate of the storage transistor M2 is proportional to the capacitance of the capacitor C1, so the width of the gate of the storage transistor M2 is designed larger than that of gates of the read pass transistor M3 and the write pass transistor M1. The reference 2 designates an element separating region isolating the first active region and the second active region. The reference 5 indicates both side portions of the gates 4A, 4B and 4C in the active regions A1, A2. C-1 is a contact hole between the source of the read pass transistor M3 and the read bit lines WL1. C-2 is a contact hole between the source of the storage transistor M2 and the Vss voltage terminal. C-3 is a contact hole between the source of the write pass transistor M1 and the bit line BL1. C-4 is a contact hole between the gate of the storage transistor M2 and the drain of the write pass transistor M1.
FIG. 3 is a sectional view along III-III' of FIG. 2. With reference to FIG. 3, a method for manufacturing DRAM as shown in FIG. 1 and FIG. 2 will be explained.
A device isolating region 2 for separating the first active region A1 and the second active region A2 is formed on a part of the semiconductor substrate 1. A gate oxide and polysilicon are successively deposited over the substrate 1, and then patterned in a known etching method to form gate oxides 3A, 3B, 3C and gates 4A, 4B, 4C. As mentioned above, a width of the gate 4B of the storage transistor M2 is larger than those of the gates 4A, 4C of the other transistors M1, M3. Thereafter, N type of impurity ions are implanted to the substrate on which the gates are formed, forming junction regions 5-1, 5-2, 5-3, 5-4, 5-5 of the respective transistor. The junction region 5-2 is a common junction region of the storage transistor M2 and the read pass transistor M3.
An insulating interlayer 6 provided with contact holes C-1, C-2, C-3 exposing the junction regions 5-1, 5-3, 5-5, is formed on the resultant having the transistors M1, M2, M3. Thereafter, metal wires 7-1, 7-2, 7-3 contacting with the junction regions via contact holes are formed.
As known from the above, in order to produce the DRAM having three transistors as shown in FIG. 2, four-contacts holes C-1, C-2, C-3, C-4 should be required. Accordingly, area for such DRAM is increased, so an integrated density of the semiconductor device is degraded.
Further, since a pitch between the metal wires 7-1, 7-2, 7-3 is smaller and smaller with the high integrated density of the semiconductor device, a reliability of the semiconductor device is debased.